LC87F06J2A Datasheet, PDF (18/32 Pages) Sanyo Semicon Device – CMOS IC FROM 192K byte, RAM 8192 byte on-chip 8-bit 1-chip Microcontroller

LC87F06J2A
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter
Frequency
Low level
pulse width
High level
Pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
Symbol
tSCK(5)
tSCKL(5)
Pins/
Remarks
SCK2
(SI2P2)
Conditions
• See Fig. 6.
VDD[V]
tSCKH(5)
tSCKHA(5a)
tSCKHA(5b)
tSCK(6)
tSCKL(6)
tSCKH(6)
tSCKHA(6a)
SCK2
(SI2P2),
SCK2O
(SI2P3)
tSCKHA(6b)
tsDI(3)
thDI(3)
SI2(SI2P1),
SB2(SI2P1)
• Continuous data
transmission/reception mode
of SIO0 is not in use
simultaneous.
• Universal remote control
transmitter is not in use
simultaneous.
• See Fig. 6.
• (Note 4-3-2)
• Continuous data
transmission/reception mode
of SIO0 is in use simultaneous.
• Universal remote control
transmitter is in use
simultaneous.
• See Fig. 6.
• (Note 4-3-2)
• CMOS output selected.
• See Fig. 6.
2.7to 5.5
• Continuous data
transmission/reception mode
of SIO0 is not in use
simultaneous.
• Universal remote control
transmitter is not in use
simultaneous.
• CMOS output selected.
• See Fig. 6.
• Continuous data
transmission/reception
mode of SIO0 is in use
simultaneous.
• Universal remote control
transmitter is in use
simultaneous.
• CMOS output elected.
• See Fig. 6.
• Must be specified with respect
to rising edge of SIOCLK
• See fig. 6.
2.7 to 5.5
2.7 to 5.5
min
2
1
1
4
10
4/3
tSCKH(6)
+(5/3)
tCYC
tSCKH(6)
+(5/3)
tCYC
0.03
0.03
Specification
typ
max
1/2
1/2
tSCKH(6)
+(10/3)
tCYC
tSCKH(6)
+(28/3)
tCYC
unit
tCYC
tSCK
tCYC
Output delay time tdDO(5)
SO2(SI2P0) • Must be specified with respect
µs
SB2(SI2P1)
to falling edge of SIOCLK
• Must be specified as the time
to the beginning of output state
change in open drain output
2.7 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
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