LC78711E Datasheet, PDF (12/43 Pages) Sanyo Semicon Device – Graphics Display Processor

LC78711E
Function Overview
1. Crystal clock oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSCO
The XIN1 and XOUT1 pins are connections for an NTSC 14.31818-MHz crystal element, and the XIN2 and XOUT2
pins are connections for a PAL 17.734476-MHz crystal element. The N/P1 pin switches the LC78711E RGB encoder
block between NTSC and PAL modes, and the N/P2 pin switches the decoder block between NTSC and PAL modes.
The FSCO pin outputs a clock signal that is the crystal oscillator frequency divided by 4. The table below enumerates
the pin states vs. the LC78711E operating modes.
XIN1, XOUT1
14.31818 MHz
*
14.30244 MHz
XIN2, XOUT2
*
17.734476 MHz
*
N/P1
H
L
L
N/P2
H
L
H
TV format
NTSC/M
PAL/GBIDH
PAL/M
FSCO
3.579545 MHz
4.433619 MHz
3.575611 MHz
2. Display format; N/P1, N/P2, LINE, CSYNC, SON, 4FSC2, FSCIN, VRESET, HRESET, YS, PALID
• The LC78711E supports both NTSC and PAL modes, with the N/P1 and N/P2 pins being used to set the mode. See
item (1) above for the pin states in the NTSC and PAL modes. The LINE pin switches the number of scan lines in a
1-V period.
• The SON, 4FSC2, FSCIN, VRESET, HRESET, YS, and PALID pins are used with the superimpose function. The
4FSC2 pin inputs a 4 × fsc frequency, and the FSCIN pin inputs the fsc frequency. The VRESET and HRESET
pins input the external video signal VSYNC and HSYNC. The internal V and H counters are reset on the falling
edges of these signals, respectively. The image may be disrupted if the 4FSC2 signal is not locked with the
VRESET and HRESET signals. The YS pin is used to switch the video signal. The PALID pin is used for burst
waveform phase matching in PAL mode.
3. DRAM interface
Interface pins: A0 to A7, DB0 to DB3, RAS, CAS, WE, OE
An external 64k × 4-bit DRAM must be used.
4. Video outputs: VIDEO1, VIDEO2
The luminance signal can be acquired from the VIDEO1 pin.
The chrominance signal can be acquired from the VIDEO2 pin.
No. 5476-12/43