S8S3122X16 Datasheet, PDF (9/44 Pages) Samsung semiconductor – 256K x 16 SDRAM

S8S3122X16
Parameter
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Symbol
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
version
-TCR2 -TCR1
10
10
20
20
20
20
20
20
48
48
100
70
70
Unit
ns
ns
ns
ns
ns
us
ns
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS Latency=3
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
CAS Latency=2
Output data
CAS Latency=3
CLK high pulse width
CAS Latency=2
CLK low pulse width
CAS Latency=3
CAS Latency=2
Input setup time
CAS Latency=3
CAS Latency=2
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS Latency=3
CAS Latency=2
-TCR2
Symbol
-TCR1
Unit Note
Min Max Min Max
10
10
tCC
1000
1000 ns 1
10
12
tSAC
-
6
-
6
ns 1, 2
-6
-8
tOH 2.5 - 2.5 - ns 2
tCH
3 - 3.5 - ns 3
tCL
3 - 3.5 - ns 3
tSS
2 - 2.5 - ns 3
tSH
1
-
1
- ns 3
tSLZ
1
-
1
- ns 2
-6
-
6
tSHZ
ns
-
6
-
8
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Ver 0.0 Sep. '01