S8S3122X16 Datasheet, PDF (7/44 Pages) Samsung semiconductor – 256K x 16 SDRAM

S8S3122X16
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Sym-
bol
Test Condition
CAS
Latency
Version
-TCR2 -TCR1
Unit
Note
Operating Current
(One Bank Active)
ICC1
Burst Length =1
tRC≥tRC(min)
Io = 0 mA
3
100 90
mA 2
2
100 90
Precharge Standby Cur-
rent in power-down mode
ICC2P CKE≤VIL(max), tCC = 15ns
ICC2PS CKE & CLK≤VIL(max), tCC = ∞
2
mA
2
Precharge Standby Current
in non power-down mode
ICC2N
ICC2NS
CKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable
15
mA
5
Active Standby Current
in power-down mode
ICC3P CKE≤VIL(max), tCC = 15ns
ICC3PS CKE & CLK≤VIL(max), tCC = ∞
3
mA
3
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
CKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3NS
CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable
25
mA
15
mA
Operating Current
(Burst Mode)
Io = 0 mA
ICC4
Page Burst 2Banks Activated
tCCD = 2CLKs
3
100 100
mA 2
2
95
95
Refresh Current
ICC5
Self Refresh Current
ICC6
tRC≥tRC(min)
CKE≤0.2V
3
100 90
mA 3
2
100 90
2
mA
Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 16ms. Addresses are changed only one time during tcc(min).
Ver 0.0 Sep. '01