S8S3122X16 Datasheet, PDF (11/44 Pages) Samsung semiconductor – 256K x 16 SDRAM

S8S3122X16
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA
W.B.L
A8/AP
A7
TM
A6
A5
A4
CAS Latency
CMOS SDRAM
A3
A2
A1
A0
BT
Burst Length
A8/AP
0
0
1
1
BA
0
1
Test Mode
A7
Type
0
Mode Register Set
1
Reserved
0
Reserved
1
Reserved
Write Burst Length
Length
Burst
Single Bit
CAS Latency
Burst Type
Burst Length
A6 A5 A4 Latency A3
Type
A2 A1 A0 BT = 0 BT = 1
0
0
0 Reserved 0 Sequential 0 0 0
1
1
0
0
1
-
1 Interleave 0 0 1
2
2
0
1
0
2
01 0
4
4
0
1
1
3
01 1
8
8
1
0
0 Reserved
1 0 0 Reserved Reserved
1
0
1 Reserved
1 0 1 Reserved Reserved
1
1
0 Reserved
1 1 0 Reserved Reserved
1
1
1 Reserved
1 1 1 Full Page Reserved
Full Page Length : x4 (512), x8 (256), x16 (256)
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If BA is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Ver 0.0 Sep. '01