K4S281633D-RL Datasheet, PDF (9/10 Pages) Samsung semiconductor – 8Mx16 SDRAM 54CSP

K4S281633D-RL(N)
Preliminary
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Register
COMMAND
Mode Register Set
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10 /AP
A11,
A9 ~A0
Note
H
X
LL
L
L
X
OP CODE
1, 2
Auto Refresh
H
3
H
LL
L
H
X
X
Entry
L
3
Refresh
Self
Refresh
Exit
LH
H
H
L
H
X
X
3
HX
XX
3
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Write &
Auto Precharge Disable
Column Address _{Auto Precharge Enable}
H
Burst Stop
H
Bank Selection
Precharge
H
All Banks
X
LL
HHX
V
X
LH
L
H
X
V
X
LH
L
L
X
V
X
LH
H
L
X
V
X
LL
H
L
X
X
Row Address
L
Column
Address
H
(A0~ A8)
L
Column
Address
H
(A0~ A8)
X
L
X
H
4
4, 5
4
4, 5
6
HX
XX
Clock Suspend or
Active Power Down
Entry
H
L
X
LV
VV
X
Exit
L
H
XX
XX
X
HX
XX
Entry
H
L
X
LH
H
H
Precharge Power Down Mode
X
HX
XX
Exit
L
H
X
LV
VV
DQM
No Operation Command
H
X
V
X
7
HX
XX
H
X
X
X
LH
H
H
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code
A0 ~ A 11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A 10 /AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 0.6 Nov. 2001