K4S281633D-RL Datasheet, PDF (3/10 Pages) Samsung semiconductor – 8Mx16 SDRAM 54CSP

K4S281633D-RL(N)
2M x 16Bit x 4 Banks SDRAM in 54CSP
Preliminary
CMOS SDRAM
FEATURES
• 3.0V & 3.3V power supply.
• LVTTL compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation..
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70 °C).
Extended Temperature Operation (-25°C ~ 85°C).
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K4S281633D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq. Interface Package
K4S281633D-RL/N75
133MHz(CL=3)
100MHz(CL=2)
K4S281633D-RL/N1H 100MHz(CL=2)
K4S281633D-RL/N1L 100MHz(CL=3)^*1
LVTTL
54 CSP
-RN ; Low Power, Operating Temperature : -25’C~85’C.
-RL ; Low Power, Operating Temperature : -25’C~70’C.
Note : 1. In case of 40MHz Frequency, CL1 can be supported.
Data Input Register
CLK
ADD
Bank Select
2M x 16
2M x 16
2M x 16
2M x 16
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE LDQM UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.6 Nov. 2001