K4S281633D-RL Datasheet, PDF (7/10 Pages) Samsung semiconductor – 8Mx16 SDRAM 54CSP

K4S281633D-RL(N)
Preliminary
CMOS SDRAM
AC OPERATING TEST CONDITIONS (VDD = 2.7V ~ 3.6V, TA =-25°C ~ 70°C (Commercial), -25°C ~ 85°C (Extended))
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
0.5 x VDDQ
tr/tf = 1/1
0.5 x VDDQ
See Fig. 2
Unit
V
V
ns
V
VDDQ
Vtt = 0.5 x VDDQ
Output
870 Ω
1200 Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
30pF
Output
Z0 = 50Ω
50 Ω
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
Unit
- 75
-1H
-1L
Row active to row active delay
tRRD (min)
15
20
20
ns
RAS to CAS delay
Row precharge time
tRCD (min)
20
20
24
ns
tRP(min)
20
20
24
ns
Row active time
tRAS(min)
45
50
60
ns
tRAS(max)
100
us
Row cycle time
Last data in to row precharge
tR C(min)
65
70
84
ns
tRDL(min)
2
CLK
Last data in to Active delay
tDAL (min)
2 CLK + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
Last data in to burst stop
tBDL (min)
1
CLK
Col. address to col. address delay
tCCD (min)
1
CLK
CAS latency=3
2
Number of valid output data
CAS latency=2
1
ea
CAS latency=1
-
0
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note
1
1
1
1
1
2
2
2
3
4
Rev. 0.6 Nov. 2001