MC56U032DCCA Datasheet, PDF (43/64 Pages) Samsung semiconductor – Dual Voltage MultiMediaCard Specification

MultiMediaCard^TM
All timing diagrams use the following schematics and abbreviations:
S
T
P
E
Z
D
*
CRC
Start bit (= ‘0’)
Transmitter bit (Host = ‘1’, Card = ‘0’)
One-cycle pull-up (= ‘1’)
End bit (=1)
High impedance state (-> = ‘1’)
Data bits
Repetition
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
RCMD respectively RDAT. Actively driven P-bits are less sensitive to noise superposition.
Timing Values
NCR
NID
NAC
NRC
NCC
NWR
NST
Min
Max
Unit
2
64
Clock cycles
5
5
Clock cycles
2
10*(TAAC*Fop+1
00*NSAC)
Clock cycles
8
--
Clock cycles
8
--
Clock cycles
2
--
Clock cycles
2
2
Clock cycles
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :
Command Response Timing (Identification Mode)
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevalent for all host commands followed by a response, except CMD1,CMD2 and CMD3 :
Command Response Timing (Data Transfer Mode)
43