MC56U032DCCA Datasheet, PDF (18/64 Pages) Samsung semiconductor – Dual Voltage MultiMediaCard Specification

MultiMediaCard^TM
rising and falling edges). If the host does not allow the switchable R_OD implementation, a fix R_CMD can
be used. Consequently the maximum operating implementation, a fix R_CMD can be used. Consequently
the maximum operating frequency in the open drain mode has to be reduced in this case.
4.4 SPI Bus Topology
4.4.1 SPI Interface Concept
The Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found
on certain Motorola micro-controllers. The MultiMediaCard SPI interface is compatible with SPI hosts
available on the market. As any other SPI device the MultiMediaCard SPI channel consists of the
following 4 signals:
- CS : Host to card chip select signal
- CLK : Host to card clock signal
- DataIn : Host to card data signal
- DataOut : Card to host data signal
Another SPI common characteristic, which is implemented in the MultiMediaCard card as well, is byte
transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal. The SPI
standard defines the physical link only and not the complete data transfer protocol. The MultiMediaCard
uses a subset of the MultiMediaCard protocol and command set.
4.4.2 SPI Bus Topology
The MultiMediaCard card identification and addressing algorithms are replaced by hardware Chip Select
(CS) signal. There are no broadcast commands. A card (slave) is selected, for every command, by
asserting (active low) the CS signal (see Figure 4-3). The CS signal bust is continuously active for the
duration of the SPI transaction (command, response and data). The only exception is card-programming
time. At this time the host can de-assert the CS signal without affecting the programming process. The
bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This
eliminates the ability of executing commands while data is being read or written and, therefore,
eliminates the sequential and multi block read/write operations. The SPI channel supports only single
block read/write.
Figure 4-3 SPI Bus System
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