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K4T1G044QF Datasheet, PDF (42/46 Pages) Samsung semiconductor – 1Gb F-die DDR2 SDRAM
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K4T1G044QF
K4T1G084QF
K4T1G164QF
datasheet
Rev. 1.11
DDR2 SDRAM
20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(AC) level to the
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(AC) level to the differential data strobe crosspoint for
a falling signal applied to the device under test. DQS, DQS signals must be monotonic between VIL(DC)max and VIH(DC)min. See Figure 20.
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input sig-
nal crossing at the VIH(DC) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(DC) level for
a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL(DC)max and VIH(DC)min. See Figure 20.
DQS
DQS
tDS tDH
tDS tDH
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
Figure 20. Differential input waveform timing - tDS and tDH
22. Input waveform timing is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the
device under test. See Figure 21.
23. Input waveform timing is referenced from the input signal crossing at the VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the
device under test. See Figure 21.
CK
CK
tIS tIH
tIS tIH
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSS
Figure 21. Differential input waveform timing - tIS and tIH
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