K4T1G044QF Datasheet, PDF (17/46 Pages) Samsung semiconductor – 1Gb F-die DDR2 SDRAM

K4T1G044QF
K4T1G084QF
K4T1G164QF
datasheet
Rev. 1.11
DDR2 SDRAM
NOTE :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as V_IN ≤ V_IL(AC)max
HIGH is defined as V_IN ≥ V_IH(AC)min
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at V_REF = V_DDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
For purposes of IDD testing, the following parameters are utilized
DDR2-800
Parameter
5-5-5
CL(IDD)
5
tRCD(IDD)
12.5
tRC(IDD)
57.5
tRRD(IDD)-x4/x8
7.5
tRRD(IDD)-x16
10
tCK(IDD)
2.5
tRASmin(IDD)
45
tRP(IDD)
12.5
tRFC(IDD)
127.5
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
DDR2-800
6-6-6
6
15
60
7.5
10
2.5
45
15
127.5
DDR2-667
5-5-5
5
15
60
7.5
10
3
45
15
127.5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during
DESELECTs. IOUT = 0mA
Timing Patterns for 8bank devices x4/ x8
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Timing Patterns for 8bank devices x16
-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
-DDR2-800 6/6/6 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
-DDR2-800 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
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