K4T1G044QF Datasheet, PDF (24/46 Pages) Samsung semiconductor – 1Gb F-die DDR2 SDRAM

K4T1G044QF
K4T1G084QF
K4T1G164QF
datasheet
Rev. 1.11
DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V_REF. In differential mode, these
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to V_SS
through a 20 Ω to 10 kΩ resistor to insure proper operation.
DQS
DQS
DQ
DM
DQS
tDQSH
tDQSL
DQS
tWPRE
V_IH(AC)
D
V_IL(AC)
tDS
DMin
D
tDS
V_IH(AC)
DMin
V_IL(AC)
V_IH(DC)
D
V_IL(DC)
tDH
DMin
Figure 5. Data Input (Write) Timing
tWPST
D
tDH
V_IH(DC)
DMin
V_IL(DC)
tCH
tCL
CK
CK/CK
CK
DQS/DQS
DQ
DQS
DQS
tRPRE
tDQSQ(max)
Q
tQH
Q
Q
tDQSQ(max)
Figure 6. Data Output (Read) Timing
tRPST
Q
tQH
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to V_SS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
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