K4S280832K Datasheet, PDF (4/15 Pages) Samsung semiconductor – 128Mb K-die SDRAM Specification

K4S280832K
K4S281632K
4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
Synchronous DRAM
1.0 Features
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
• 54pin TSOP II Lead-Free and Halogen-Free package
• RoHS compliant
2.0 General Description
The K4S280832K / K4S281632K is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by
8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows
precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
3.0 Ordering Information
Part No.
K4S280832K-U^*1C/L75
K4S281632K-UC/L50
K4S281632K-UC/L60
K4S281632K-UC/L75
Orgainization
16Mb x 8
8Mb x 16
8Mb x 16
8Mb x 16
Max Freq.
133MHz (CL=3)
200MHz(CL=3)
166MHz (CL=3)
133MHz (CL=3)
Interface
LVTTL
Note 1 : 128Mb K-die SDR DRAMs support Lead-Free & Halogen-Free package with Lead-Free package code(-U).
Package
54pin TSOP(II)
Lead-Free & Halogen-Free^*1
Organization
16Mx8
8Mx16
Row Address
A0~A11
A0~A11
Column Address
A0-A9
A0-A8
Row & Column address configuration
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Rev. 1.23 March 2009