K4S280832K Datasheet, PDF (11/15 Pages) Samsung semiconductor – 128Mb K-die SDRAM Specification

K4S280832K
K4S281632K
13.0 AC Operating Test Conditions
Parameter
Input levels (V_IH/V_IL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Synchronous DRAM
(V_DD = 3.3V ± 0.3V, T_A = 0 to 70°C)
Unit
V
V
ns
V
Output
870Ω
3.3V
1200Ω
50pF
V_OH (DC) = 2.4V, I_OH = -2mA
V_OL (DC) = 0.4V, I_OL = 2mA
Output
Z0 = 50Ω
V_TT = 1.4V
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
14.0 Operating AC Parameter
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
Unit
50 (x16 only) 60 (x16 only)
75
Row active to row active delay
tRRD(min)
10
12
15
ns
RAS to CAS delay
tRCD(min)
15
18
20
ns
Row precharge time
tRP(min)
15
18
20
ns
Row active time
tRAS(min)
40
42
45
ns
tRAS(max)
100
us
Row cycle time
tRC(min)
55
60
65
ns
Last data in to row precharge
tRDL(min)
2
CLK
Last data in to Active delay
tDAL(min)
2 CLK + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
Last data in to burst stop
tBDL(min)
1
CLK
Col. address to col. address delay
tCCD(min)
1
CLK
Number of valid output data
CAS latency=3
CAS latency=2
2
ea
-
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the
next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
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Rev. 1.23 March 2009