M368L6523CUS Datasheet, PDF (3/25 Pages) Samsung semiconductor – DDR SDRAM Unbuffered Module

256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
184Pin Unbuffered DIMM based on 512Mb C-die (x8, x16)
Ordering Information
Part Number
M368L3324CUS-C(L)CC/B3
M368L6523CUS-C(L)CC/B3
M381L6523CUM-C(L)CC/B3
M368L2923CUN-C(L)CC/B3
M381L2923CUM-C(L)CC/B3
Density
256MB
512MB
512MB
1GB
1GB
Organization
32M x 64
64M x 64
64M x 72
128M x 64
128M x 72
Component Composition
32Mx16 (K4H511638C) * 4EA
64Mx8 (K4H510838C) * 8EA
64Mx8 (K4H510838C) * 9EA
64Mx8 (K4H510838C) * 16EA
64Mx8 (K4H510838C) * 18EA
Height
1,250mil
1,250mil
1,250mil
1,250mil
1,250mil
Operating Frequencies
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
CC(DDR400@CL=3)
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided
• SSTL_2 Interface
• 66pin TSOP II Pb-Free package
• RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.0 February. 2005