DS_S1M8837 Datasheet, PDF (28/29 Pages) Samsung semiconductor – FRACTIONAL-N RF/INTEGER-N IF DUAL PLL

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PCB LAYOUT GUIDE
In doing PCB layouts for S1M8836/37, we recommend that you apply the following design guide to your
handsets, thus improving the phase noise and reference spurious performances of the phones.
1. The S1M8836/37 has external four power supply pins to supply on-chip bias, each for analog and digital
blocks of RF and IF PLLs. Basically in doing PCB layout, it is important that power supply lines should be
separated from one another and thus coupling noises through the voltage supply lines can be minimized. If
you have some troubles with the direction to separate, you can choose the following recommendations for
your convenience;
• Tying analog power lines, V_DDRF and V_DDIF, is possible.
• Tying digital power lines, V_P1 and V_P2, is possible.
• A point connecting the analog and digital power lines should be near to battery line as close as possible.
It minimizes coupling noise effects from a digital switching noise into analog blocks. We also
recommend that a passive RC low pass filter(R(22Ω),C(100nF)) be utilized for suppressing high
frequency noise on the analog power supply line and reducing any digital noise couplings.
2. VCO power lines should be well separated from those of PLL because VCO is generally a very sensitive
device from power line noises and PLL is a digital noise generator.
3. For more improvement of reference spurious performance, it is recommended that the LPF ground be tied to
the PLL ground, not the VCO ground.
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