DS_S1M8837 Datasheet, PDF (22/29 Pages) Samsung semiconductor – FRACTIONAL-N RF/INTEGER-N IF DUAL PLL

S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
IF Power down mode table
W1[20]
0
0
1
1
W1[19]
0
1
0
1
Power down mode status
IF PLL active
IF PLL active, only charge pump to TRISTATE
Asynchronous power down
Synchronous power down
Programmable Counter Reset Control
Control Words
IF_CTL_WORD
RF_CTL_WORD
Control bits
W1[21]
W4[21]
Acronym
IF_CNT_RST
RF_CNT_RST
LOW (0)
HIGH (1)
normal operation IF counter reset
normal operation RF counter reset
Counter Reset mode resets R & N counters.
Comments
IF
RF
RF Fractional-N selection
Control Words Control bits
RF_CTL_WORD W4[19]
Acronym
Frac_N_SEL
LOW (0)
reserved
HIGH (1)
Fractional-N mode
Comments
RF;PLL mode
selection
CMOS Output Control
Control Words
CMOS
Control bits
W2[21]
W2[20]
W2[19]
Acronym
Speedy Lock
OUT1
OUT0
LOW (0)
CMOS output
voltage LOW
voltage LOW
HIGH (1)
Speedy Lock
mode
voltage HIGH
voltage HIGH
Comments
pin #23
pin #24
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low
and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a
low impedance(< 150Ω) while a high charge pump gain(≥ 8X) is selected and otherwise to a tri-state. For using a
programmable CMOS output, the CMOS output bit(W2[21]= LOW) should be activated and then the desired logic
level should be programmed with the control bits W2[19] for OUT0 and W2[20] for OUT1.
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