DS_S1M8837 Datasheet, PDF (15/29 Pages) Samsung semiconductor – FRACTIONAL-N RF/INTEGER-N IF DUAL PLL

FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Data Bit Map (DATA[21:2]) (Continued)
Control Words
IF_CTL_WORD
Control
bits
W1[21]
W1[20]
W1[19]
Acronym
IF_CNT_RST
PWDN_IF
PWDN
CMOS
W2[21] Speedy_Lock
IF_CP_WORD
W2[20]
W2[19]
W2[18]
OUT1
OUT0
IF_CP_GAIN
foLD
W2[17] IF_PFD_POL
W3[21:18]
foLD
RF_CP_WORD W3[17:14] RF_CP_LVL
RF_CTL_WORD
W3[13]
W4[21]
W4[20]
W4[19]
RF_PFD_POL
RF_CNT_RST
PWDN_RF
Frac-N_SEL
LOW (0)
HIGH (1)
Comments
normal operation
power up
asynchronous
power down
CMOS output
voltage LOW
voltage LOW
1X
IF counter reset
power down
synchronous
power down
Speedy_Lock
mode
voltage HIGH
voltage HIGH
8X
negative slope
positive slope
select LDs and monitoring mode of
internal counters. (FoLD control for
control codes in detail)
select 16-level charge pump current (RF
charge pump gain for control codes in
detail)
negative slope
positive slope
normal operation
RF counter reset
power up
power down
Integer-N mode
Fractional-N
mode
IF
IF
RF and IF
pin #23
pin #24
IF charge
pump
IF PFD
Lock
Detector(LD),
Test mode
RF charge
pump
RF PFD
RF
RF
RF; PLL mode
selection
— Counter Reset mode resets R & N counters.
— IF charge pump current can be selected to high current(8X) or low current(1X) mode.
— In the Speedy_Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active
low and tri-state. The Speedy_Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND
with a low impedance(< 150Ω) while a high charge pump gain( ≥ 8X) is selected and otherwise to the
TRISTATE.
— For using a programmable CMOS output, the CMOS output bit(W2[21]=L) should be activated and then the
desired logic level should be programmed with the control bits W2[19] for OUT0 and W2[20] for OUT1.
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