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DS_S1M8837 Datasheet, PDF (21/29 Pages) Samsung semiconductor – FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
VCO Characteristics
(1)
VCO
Output
Frequency
(2)
VCO Input
Voltage
S1M8836/37
Program Mode Control
Power down mode operation
Control Words
IF_CTL_WORD
Control bits
W1[20]
W1[19]
Acronym
PWDN_IF
PWDN
RF_CTL_WORD
W4[20]
PWDN_RF
LOW (0)
power up
asynchronous
power down
power up
HIGH (1)
power down
synchronous power
down
power down
Comments
IF
RF and IF
RF
Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits
(PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the
program control bits determine the state of power control. Power down forces all the internal analog blocks to be
deactivated and the charge pump output to be in a TRISTATE. The oscillator buffer is powered down when the
power down bits (W4[20] and W1[20]) become HIGH. The control register and R/N counters, however, remains
active for permitting serial programming and is capable of loading and latching in data during the power down.
There are synchronous and asynchronous power-down modes for S1M8836/37. The power-down bit W1[19] is
used to select between synchronous and asynchronous power-down. Synchronous power-down mode occurs if
W1[19] bit is HIGH and then the power down bit (W4[20] or W1[20]) becomes HIGH. In the synchronous power
down mode, the power-down function will go into power-down mode upon the completion of a charge pump pulse
event because it is synchronized with the charge pump and thus can diminish undesired frequency jumps.
Asynchronous power down mode occurs if W1[19] bit is LOW and then the power down bit (W4[20] or W1[20])
becomes HIGH. Activation of the asynchronous function will go into power-down mode immediately.
RF Power down mode table
W4[20]
0
0
1
1
W1[19]
0
1
1
1
Power down mode status
RF PLL active
RF PLL active, only charge pump to TRISTATE
Asynchronous power down
Synchronous power down
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