M378T3354BG Datasheet, PDF (2/23 Pages) Samsung semiconductor – DDR2 Unbuffered SDRAM MODULE

256MB,512MB,1GB Unbuffered DIMMs
DDR2 Unbuffered DIMM Ordering Information
Part Number
Density Organization Component Composition
x64 Non ECC
M378T3354BG(Z)0-CD5/CC
256MB
32Mx64
32Mx16(K4T51163QB)*4
M378T6553BG(Z)0-CD5/CC
512MB
64Mx64
64Mx8(K4T51083QB)*8
M378T2953BG(Z)0-CD5/CC
1GB
128Mx64
64Mx8(K4T51083QB)*16
x72 ECC
M391T6553BG(Z)0-CD5/CC
512MB
64Mx72
64Mx8(K4T51083QB)*9
M391T2953BG(Z)0-CD5/CC
1GB
128Mx72
Note: “Z” of Part number stand for Lead-free products.
64Mx8(K4T51083QB)*18
DDR2 SDRAM
Number of
Rank
Height
1
30mm
1
30mm
2
30mm
1
30mm
2
30mm
Features
• Performance range
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
D5(DDR2-533)
400
533
-
4-4-4
CC(DDR2-400)
400
400
-
3-3-3
Unit
Mbps
Mbps
Mbps
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f_CK for 400Mb/sec/pin, 267MHz f_CK for 533Mb/sec/pin
• 4 Bank
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refesh Period 7.8us at lower then T_CASE 85×C, 3.9us at 85×C < T_CASE < 95 ×C
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 64Mx8, 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Rev. 1.2 Jan. 2005