M378T3354BG Datasheet, PDF (13/23 Pages) Samsung semiconductor – DDR2 Unbuffered SDRAM MODULE

256MB,512MB,1GB Unbuffered DIMMs
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
DDR2 SDRAM
Symbol Proposed Conditions
IDD0
Operating one bank active-precharge current;
tCK ₌ tCK(IDD), tRC ₌ tRC(IDD), tRAS ₌ tRASmin(IDD); _{CKE is HIGH, CS\ is HIGH between valid com-}
mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRC} = ^tRC (IDD), ^tRAS = ^{tRASmin(IDD), tRCD}
= ^tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING;
Data pattern is same as IDD4W
IDD2P
Precharge power-down current;
All banks idle; tCK = ^tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
IDD2Q
Precharge quiet standby current;
All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STA-
BLE; Data bus inputs are FLOATING
IDD2N
Precharge standby current;
All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD3P
Active power-down current;
All banks open; ^tCK = ^tCK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
IDD3N
Active standby current;
All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^tRAS-
max(IDD), ^tRP = ^tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; ^tCK = ^{tCK(IDD), tRAS}
= ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
IDD5B
Burst auto refresh current;
tCK ₌ tCK(IDD); _{Refresh command at every} tRFC(IDD) _{interval; CKE is HIGH, CS\ is HIGH between valid}
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD6
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
Low Power
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} =
tCK(IDD), tRC ₌ tRC(IDD), tRRD ₌ tRRD(IDD), tRCD _{= 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between}
valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;
Refer to the following page for detailed timing conditions
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
Rev. 1.2 Jan. 2005