M378T3354BG Datasheet, PDF (18/23 Pages) Samsung semiconductor – DDR2 Unbuffered SDRAM MODULE

256MB,512MB,1GB Unbuffered DIMMs
Parameter
Control & Address input
pulse width for each input
DQ and DM input pulse
width for each input
Data-out high-impedance
time from CK/CK
DQS low-impedance time
from CK/CK
DQ low-impedance time
from CK/CK
DQS-DQ skew for DQS and
associated DQ signals
DQ hold skew factor
DQ/DQS output hold time
from DQS
Write command to first DQS
latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK
setup time
DQS falling edge hold time from
CK
Mode register set command
cycle time
Write postamble
Write preamble
Address and control input
hold time
Address and control input
setup time
Read preamble
Read postamble
Active to active command
period for 1KB page size
products
Active to active command
period for 2KB page size
products
Four Activate Window for
1KB page size products
Four Activate Window for
2KB page size products
CAS to CAS command
delay
Symbol
tIPW
DDR2-533
min
max
0.6
x
DDR2-400
min
max
0.6
x
tDIPW
0.35
x
0.35
x
tHZ
x
tAC max
x
tAC max
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
tLZ(DQ)
2* tACmin tAC max 2* tACmin
tAC max
tDQSQ
x
300
x
350
tQHS
tQH
x
400
x
450
tHP - tQHS
x
tHP - tQHS
x
tDQSS
WL-0.25
WL+0.25 WL-0.25
WL+0.25
tDQSH
0.35
x
0.35
x
tDQSL
0.35
x
0.35
x
tDSS
0.2
x
0.2
x
tDSH
0.2
x
0.2
x
tMRD
2
x
2
x
tWPST
0.4
0.6
0.4
0.6
tWPRE
0.35
x
0.35
x
tIH
375
x
475
x
tIS
250
x
350
x
tRPRE
0.9
1.1
0.9
1.1
tRPST
0.4
0.6
0.4
0.6
tRRD
7.5
x
7.5
x
tRRD
10
x
10
x
tFAW
37.5
37.5
tFAW
50
50
tCCD
2
2
Units Notes
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
tCK
tCK
ns
ns
ns
ns
tCK
DDR2 SDRAM
Rev. 1.2 Jan. 2005