K4T1G044QC Datasheet, PDF (18/26 Pages) Samsung semiconductor – 1Gb C-die DDR2 SDRAM Specification

K4T1G044QC
K4T1G084QC
DDR2 SDRAM
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
DDR2-800
min max
DDR2-667
min max
DDR2-533
min max
DDR2-400
min max
Units Notes
DQ output access time from CK/CK
tAC
- 400
400
-450
+450
-500
+500
-600
+600
ps
DQS output access time from CK/CK
tDQSCK
- 350
350
-400
+400
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
min(tCL,
min(tCL,
min(tCL,
min(tCL,
tHP
x
x
x
x
ps 20,21
tCH)
tCH)
tCH)
tCH)
Clock cycle time, CL=x
tCK
2500
8000
3000
8000
3750
8000
5000
8000
ps
24
DQ and DM input hold time
15,16,
tDH(base) 125
x
175
x
225
x
275
x
ps
17,20
DQ and DM input setup time
tDS(base)
50
x
100
x
100
x
150
15,16,
x
ps
17,21
Control & Address input pulse width for each input tIPW
0.6
x
0.6
x
0.6
x
0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
x
0.35
x
0.35
x
0.35
x
tCK
Data-out high-impedance time from CK/CK
tHZ
x
tAC max
x
tAC max
x
tAC max
x
tAC max ps
DQS low-impedance time from CK/CK
tLZ(DQS) tAC min tAC max tAC min tAC max tAC min tAC max tAC min tAC max ps
27
DQ low-impedance time from CK/CK
2*tAC
2*tAC
2* tACmi
2* tACmi
tLZ(DQ)
tAC max
tAC max
tAC max
tAC max ps
27
min
min
n
n
DQS-DQ skew for DQS and associated DQ signals tDQSQ
x
200
x
240
x
300
x
350
ps
22
DQ hold skew factor
tQHS
x
300
x
340
x
400
x
450
ps
21
DQ/DQS output hold time from DQS
tHP -
tHP -
tHP -
tHP -
tQH
x
x
x
x
ps
tQHS
tQHS
tQHS
tQHS
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
19
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
0.35
x
tCK
Address and control input hold time
tIH(base)
250
x
275
x
375
x
475
14,16,
x
ps
18,23
Address and control input setup time
tIS(base)
175
x
200
x
250
x
350
14,16,
x
ps
18,22
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
28
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
28
Active to active command period for 1KB page size
tRRD
products
7.5
x
7.5
x
7.5
x
7.5
x
ns
12
Active to active command period for 2KB page size
tRRD
products
10
x
10
x
10
x
10
x
ns
12
Four Activate Window for 1KB page size products tFAW
35
37.5
37.5
37.5
ns
Four Activate Window for 2KB page size products tFAW
45
50
50
50
ns
CAS to CAS command delay
tCCD
2
x
2
2
2
tCK
Write recovery time
tWR
15
x
15
x
15
x
15
x
ns
Auto precharge write recovery + precharge time tDAL
WR+tRP
x
WR+tRP
x
WR+tRP
x
WR+tRP
x
tCK
23
Internal write to read command delay
tWTR
7.5
7.5
x
7.5
x
10
x
ns
33
Internal read to precharge command delay
tRTP
7.5
7.5
7.5
7.5
ns
11
tRFC +
tRFC +
tRFC +
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
10
10
10
Exit self refresh to a read command
tXSRD
200
x
200
200
200
tCK
Exit precharge power down to any non-read com-
tXP
mand
2
x
2
x
2
x
2
x
tCK
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Rev. 1.1 June 2007