BU92747XXX Datasheet, PDF (20/46 Pages) Rohm – IrDA Controller LSI built-in Ir remote control

BD92747XXX
Datasheet
●TRCR: Transmit / Receive Control Register
The TRCR register sets various environments for transmission and reception.
TRCR0: TX_EN (Transmit Enable)
When this bit is set to “1”, the transmission mode is set.
When this bit is set to “0”, all data within the FIFO buffer is transmitted, and then transmission is terminated.
When the relation between the number of registers set in the FTLV register and the FLV register (register indicating the
amount of data within the buffer) is FLV  FTLV, then TX_EN=0 is automatically set and data transmission is terminated
after all data within the FIFO buffer is transmitted.
(Do not set TX_EN and RX_EN to 1 even though this setting causes data reception to take precedence over data
transmission.)
TRCR1: RX_EN (Receive Enable)
When this bit is set to “1”, the receive mode is set.
When this bit is set to “0”, data reception is terminated. When the last data is odd byte at SIR reception,
it must be “C1” (EOF).
(When "C1" data of EOF is written on the LSB side of FIFO at the SIR mode, "00" is inserted in the MSB side by
independence and the increment does the FIFO pointer.)
In addition, when the receive mode is terminated once and set again after received data has been read at FIR reception,
the next reception is started.
(RX_CON=1and RX_EN=1, or AUTO_FLV_CP=1 and RX_EN=1, this bit doesn't have to be set to the
receiving mode again.)
TRCR2: S_EOT (Set End of Transmission)
This bit is effective in MIR and FIR mode. When This bit is set to ”1”, the next data written to the FIFO buffer
(2-byte data only) is recognized as the last data and CRC and STF are added just after that data to send a frame.
After frame transmission this bit is automatically set to “0". This bit cannot be used in SIR mode.
TRCR3: IR_PLS (IrDA Pulse)
This bit is effective in MIR mode, FIR mode and many windows transmit mode (MIR and FIR). When this bit is set to “1”,
an interaction pulse is transmitted just after the frame being transmitted. After transmission, IR_PLS is automatically set to
“0". This bit cannot be used in SIR mode.
1.6us
8.7us
Serial Infrared Ray
Interaction pulse
TRCR4: FCLR (FIFO clear)
When this bit is set to “1”, WP (Write Point) and RP (Read Point) within the FIFO buffer are initialized.
After completion of initialization, this bit is automatically set to “0".
TRCR5: MS_EN (Mode Select Enable)
This bit is used to switch the communication mode of the Rohm IrDA module RPM971/972.
When this bit is set to “1”, the operation mode of the IrDA module is changed according to the current operation mode of
BU92747XXX. Upon completion of operation, MS_EN is automatically set to “0".
When BU92747XXX has been set in the FIR mode, IrDA Module is changed to the FIR mode:
1. The IrDA PWDOWN and IrTX pins are set to “High (H)".
2. After about 200ns have elapsed, the IrDA PWDOWN pin is set to “Low (L)".
3. After about 200ns have elapsed, the IrTX pin is set to “Low (L)” for 200µs.
When BU92747XXX has been set in the SIR/MIR mode, IrDA Module is changed to the SIR mode:
1. The IrDA PWDOWN pin is set to "High (H)” and the IrTX pin is set to “Low (L)".
2. After about 200ns have elapsed, the IrDA PWDOWN pin is set to “Low (L)”.
3. After about 200ns have elapsed, the IrTX pin is set to “Low (L)” for 200µs.
(When TRCR3 and TRCR5 is set to “1” at the same time, TRCR5 takes precedence.)
TRCR6: IrPD (IrDA POWER DOWN)
When this bit is set to “1”, the IrDA PWDOWN pin is set to “Hi”.
When this bit is set to “0”, the IrDA PWDOWN pin is set to “Lo”.
At system reset, this bit is set to "1". (When TRCR5 and TRCR6 is set to “1” at the same time, TRCR6 takes precedence.)
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TSZ22111・15・001
20/20
TSZ02201-0E4E0F100020-1-2
24. June. 2015 Rev.001