BU92747XXX Datasheet, PDF (16/46 Pages) Rohm – IrDA Controller LSI built-in Ir remote control

BD92747XXX
Datasheet
●EIR: Event Identification Register
EIR indicates an interrupt source at interrupt occurrence. All 13 bits corresponds to interrupts (interrupt array) set in IER.
When an interrupt is invalid, the corresponding bits of EIR (status register) are set to “1” at event occurrence.
At system reset, all bits are reset to “0". In addition, this register is cleared to“0” when the CPU reads data in the register.
EIR0: DRX_EI (Data Receiver Event Identification)
This bit is set to “1” when one-byte received data is transmitted from the receive shift register to the FIFO buffer
in SIR mode.
EIR1:
This bit works as EOFRX_EI in SIR mode and STFRX_EI in MIR and FIR mode.
EOFRX_EI: (End of Frame Receiver Event Identification)
Sets an interrupt as a data read request when EOF (C1) data has been written to FIFO.
STFRX_EI: (Stop Flag Receiver Event Identification)
Sets an interrupt as a data read request when a Stop Flag has been detected during reception.
EIR2: TO_EI (Timeout Event Identification)
This bit is set to“1” for time-out.
EIR3: TXE_EI (Transmitter Empty Event Identification)
This bit is set to “1” when both transmissions FIFO buffer and transmission shift register are emptied and frame
transmission is completed during data transmission. （This bit is set to “1” only when FIFO buffer becomes empty by
transmitting data.
If this bit is cleared by FCLR, it remains “0”.）
EIR4: CRC_EI (CRC Error Event Identification)
This bit is set to “1” at CRC error occurrence.
EIR5: OE_EI (Overrun Error Event Identification)
This bit is set to “1” at overrun error occurrence.
EIR6: EOF_EI (End of frame Event Identification)
This bit is set to “1” when FIFO is emptied in reading the last byte (EOF <h’C1> in SIR mode or last byte in frame
information in MIR and FIR mode) of data written to FIFO in receive mode.
In many windows receive mode, interrupt occurs in every reading the last byte.
EIR7:
This bit is set to “1” as FE_EI in SIR mode, AC_IE in MIR mode or as DECE_EI in FIR mode.
FE_EI: (Framing Error Event Identification)
This bit is set to“1” when the stop bit of received data is not detected.
AC_EI: (Abort Condition Event Identification)
This bit is set to“1” when the received data of abort condition.
DECE_EI: (Decode Error Event Identification)
This bit is set to “1” when a decode error occurs during data reception.
EIR8: RDOE_EI (Read Overrun Error Event Identification)
This bit is effective in many windows receive mode (MIR and FIR) and AUTO_FLV_CP mode.
This bit is set to “1” in condition of FLVⅡ<0 as a register which tells too much reading of ex-frame data,
when read the FIFO data.
In the case, all data in FIFO is automatically reset by BU92747XXX, and it becomes FLV=FLVⅡ=0.
EIR9: DEX_EI (Data Exist Event Identification)
This bit is effective in many windows receive mode (MIR and FIR) and AUTO_FLV_CP mode.
When the setting is not done to FLV_CP=1 until the data of the next frame is received after Stop Flag of a front frame is
received, interrupt is set. In that case, all data that exists in FIFO in the hard independence is reset, and it becomes
FLV=FLVⅡ= FLVⅢ=FLVⅣ =0.
This bit is set to "1" as a frame error when the Start Flag reception of the frame will start one after another by the time
CPU finishes reading receive data after generating the RDE_EI interruption at the AUTO_ FLV_CP mode
EIR10: RDUE_EI (Read Underrun Error Event Identification)
This bit is effective in many windows receive mode (MIR and FIR).
This bit is set to "1" as a register that notifies the reading leaving of the front frame data FLVⅡ ≠ 0 to be
when the value of FLV is copied to FLVⅡ with FLV_CP=1 (TRCR13).
EIR11: WRE_EI (Write Enable Event Identification)
This bit is effective in many windows transmit mode.
This bit is set to "1" as a register which tells the CPU to be able to write next frame data in many windows transmit mode.
EIR12： RDE_EI(Read Enable Event Identification)
This bit is effective in the AUTO_FLV_CP mode. Do not set "1" in the other modes.
This bit is set to "1" as a register that notifies to read it the reception frame data at the AUTO_FLV_CP mode.
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TSZ22111・15・001
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TSZ02201-0E4E0F100020-1-2
24. June. 2015 Rev.001