BU92747XXX Datasheet, PDF (15/46 Pages) Rohm – IrDA Controller LSI built-in Ir remote control

BD92747XXX
Datasheet
●TXD / RXD: Transmit/Receive Data Register
TXD/RXD shares the same address.
TXD is accessed when transmission data is written and is used as a transmission data hold register.
When the FIFO buffer is effective, it works as the first storage register of TX_FIFO.
RXD is accessed when received data is read out and is used as a receive data storage register.
When the FIFO buffer is effective, it also works as the last storage register of RX_FIFO. Neither reading from TXD nor
writing to RXD can be performed.
●IER: Interrupt Enable Register
IER is used to control (enable) various kinds of interrupts.
All 13 bits correspond to interrupts so that they can be controlled independently.
Once system reset takes place, all the bits are set to "0". Each interrupt can be enabled by writing “1” to the corresponding
bit.
IER0: DRX_IE (Data Receiver Interrupt Enable)
When one-byte received data has been transmitted in SIR mode from the receive shift register to the FIFO buffer,
this bit sets an interrupt as a data read request.
IER1:
This bit works as EOFRX_IE in SIR mode or as STFRX_IE in MIR, FIR mode.
EOFRX_IE: (End of Frame Receiver Interrupt Enable)
Sets an interrupt as a data read request when EOF (C1) data has been written to FIFO.
STFRX_IE: (Stop Flag Receiver Interrupt Enable)
Sets a data read request when a Stop Flag has been detected during data reception.
IER2: TO_IE (Timeout Interrupt Enable)
This bit sets an interrupt for time-out.
IER3: TXE_IE (Transmitter Empty Interrupt Enable)
This bit sets an interrupt that takes place after both transmission FIFO buffer and transmission shift register are emptied
and frame transmission is completed during data transmission.
IER4: CRC_IE (CRC Error Interrupt Enable)
This bit is effective in MIR and FIR mode. It sets an interrupt that takes place at CRC error occurrence.
In SIR mode, this bit is ignored but must be set to “0".
IER5: OE_IE (Overrun Error Interrupt Enable)
This bit sets an error at overrun (Overrun error occurs when the receive FIFO buffer becomes full and
the next data is completely received in the receive register).
IER6: EOF_IE (End of Frame Interrupt Enable)
This bit sets an interrupt that takes place when FIFO is emptied in reading the last byte (EOF <h’C1> in SIR mode or
last byte in frame information in MIR and FIR mode) of data written to FIFO in receive mode.
IER7:
This bit works FE_IE in SIR mode, AC_IE in MIR mode and DECE_IE in FIR mode.
FE_IE: (Framing Error Interrupt Enable)
Sets an interrupt that occurs when the stop bit of received data is not detected.
AC_IE: (Abort Condition Interrupt Enable)
Sets an interrupt that occurs when the received data of abort condition.
DECE_IE: (Decode Error Interrupt Enable)
Sets an interrupt that occurs for a decode error during data reception.
IER8: RDOE_IE (Read Overrun Error Interrupt Enable)
This bit is effective in many windows receive mode (MIR and FIR) and Auto_FLV_CP mode.
This bit sets as a register that tells too much reading of ex-frame data, when read the FIFO data.
IER9: DEX_IE (Data Exist Interrupt Enable)
This bit is effective in many windows receive mode (MIR and FIR) and A AUTO_FLV_CP mode. Do not set "1" in the
other modes. When the setting is not done to FLV_CP=1 until the data of the next frame is received after Stop Flag of a
front frame is received, interrupt is set.
reading receive data after generating the RDE_EI interruption (FLVⅡ value becomes 0) at the AUTO_ FLV_CP mode.
IER10: RDUE_IE (Read Underrun Error Interrupt Enable)
This bit is effective in many windows receive mode (MIR and FIR). Do not set "1" in the other modes.
This bit sets as a register that notifies the reading leaving of the front frame data FLVⅡ ≠0 to be when the value of FLV
is copied to FLVⅡ with FLV_CP=1 (TRCR13).
IER11: WRE_IE (Write Enable Interrupt Enable)
This bit is effective in many windows transmit mode. Do not set "1" in the other modes.
This bit sets as a register that tells the CPU to be able to write next frame data in many windows transmit mode.
IER12： RDE_IE(Read Enable Interrupt Enable)
This bit is effective in the AUTO_FLV_CP mode. Do not set "1" in the other modes.
This bit sets as a register that notifies to read it the reception frame data at the AUTO_FLV_CP mode.
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TSZ22111・15・001
15/15
TSZ02201-0E4E0F100020-1-2
24. June. 2015 Rev.001