H8S2378 Datasheet, PDF (962/1203 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 21 Flash Memory (0.18-µm F-ZTAT Version)
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 21.4.4, Procedure Program and Storable Area for
Programming Data.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing is not executed, erasing is
executed before writing.
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is updated
in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the dummy data to be added is H'FF, the program processing period can be
shortened.
1. Select the on-chip program to be downloaded and specify a download destination
When the PPVS bit of FPCS is set to 1, the programming program is selected. Several
programming/erasing programs cannot be selected at one time. If several programs are set,
download is not performed and a download error is returned to the SS bit in DPFR. The start
address of a download destination is specified by FTDAR.
2. Program H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for download
request.
3. 1 is written to the SCO bit of FCCS and then download is executed.
To write 1 to the SCO bit, the following conditions must be satisfied.
 H'A5 is written to FKEY.
 The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned
to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of DPFR. Before the SCO bit is
set to 1, incorrect determination must be prevented by setting the one byte of the start address
(to be used as DPFR) specified by FTDAR to a value other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing. Four NOP
instructions are executed immediately after the instructions that set the SCO bit to 1.
Rev. 6.00 Jul 19, 2006 page 898 of 1136
REJ09B0109-0600