H8S2378 Datasheet, PDF (316/1203 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
φ
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
φ
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_i T₁ T₂
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)
Rev. 6.00 Jul 19, 2006 page 252 of 1136
REJ09B0109-0600