H8S2378 Datasheet, PDF (506/1203 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 9 Data Transfer Controller (DTC)
9.5.3 Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 9.6 lists the register function in block
transfer mode.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once
the specified number of transfers has ended, a CPU interrupt is requested.
Table 9.6 Register Function in Block Transfer Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Function
Designates source address
Designates destination address
Holds block size
Designates block size count
Designates transfer count
SAR
or
DAR
First block
Transfer
Block area
Nth block
DAR
or
SAR
Figure 9.8 Memory Mapping in Block Transfer Mode
Rev. 6.00 Jul 19, 2006 page 442 of 1136
REJ09B0109-0600