H8S2378 Datasheet, PDF (1125/1203 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series

Section 26 Electrical Characteristics
(5) Timing of On-Chip Peripheral Modules
Table 26.36 Timing of On-Chip Peripheral Modules
Conditions: V_CC = 3.0 V to 3.6 V, AV_CC = 3.0 V to 3.6 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS =
0 V, φ = 8 MHz to 34 MHz, T_a = −20°C to +75°C (regular specifications),
T_a = −40°C to +85°C (wide-range specifications)
Item
I/O ports
PPG
TPU
8-bit timer
WDT
SCI
Symbol Min.
Output data delay time
tPWD

Input data setup time
tPRS
25
Input data hold time
tPRH
25
Pulse output delay time
tPOD

Timer output delay time
tTOCD

Timer input setup time
tTICS
25
Timer clock input setup time tTCKS 25
Timer clock Single-edge
pulse width specification
tTCKWH 1.5
Both-edge
specification
tTCKWL 2.5
Timer output delay time
tTMOD

Timer reset input setup time tTMRS 25
Timer clock input setup time tTMCS 25
Timer clock Single-edge
pulse width specification
tTMCWH 1.5
Both-edge
specification
tTMCWL 2.5
Overflow output delay time tWOVD 
Input clock Asynchronous tScyc
4
cycle
Synchronous
6
Input clock pulse width
Input clock rising time
Input clock falling time
Transmit data delay time
Receive data setup time
(synchronous)
tSCKW
0.4
tSCKr

tSCKf

tTXD

tRXS
40
Receive data hold time
(synchronous)
tRXH
40
Max.
40


40
40



Unit Test Conditions
ns Figure 26.33
ns
ns
ns Figure 26.34
ns Figure 26.35
ns
ns Figure 26.36
tcyc

tcyc
40
ns Figure 26.37

ns Figure 26.39

ns Figure 26.38

tcyc

tcyc
40
ns Figure 26.40

tcyc Figure 26.41

0.6
tScyc
1.5
tcyc
1.5
40
ns Figure 26.42

ns

ns
Rev. 6.00 Jul 19, 2006 page 1061 of 1136
REJ09B0109-0600