H8S-2218 Datasheet, PDF (94/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 2 CPU
Table 2.1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
POP*¹, PUSH*¹
LDM*⁵, STM*⁵
MOVFPE*³, MOVTPE*³
B/W/L 5
W/L
L
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
B/W/L 19
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
W/L
TAS*⁴
B
Logic operations AND, OR, XOR, NOT
B/W/L 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
Bcc*², JMP, BSR, JSR, RTS
–
5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, –
9
NOP
Block data transfer EEPMOV
–
1
Total: 65
Legend: B: Byte size
W: Word size
L: Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. ER7 is used as a stack pointer in STM and LDM instructions. ER7, therefore, should not
be used as a saving (STM) or restoring (LDM) register.
Rev.6.00 Jun. 03, 2008 Page 46 of 698
REJ09B0074-0600