H8S-2218 Datasheet, PDF (331/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Bit Bit Name Initial value
4 BFA
0
3 MD3
0
2 MD2
0
1 MD1
0
0 MD0
0
Section 9 16-Bit Timer Pulse Unit (TPU)
R/W Description
R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated. In
channels 1 and 2, which have no TGRC, bit 4 is reserved.
It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
R/W Modes 3 to 0
R/W These bits are used to set the timer operating mode.
R/W MD3 is a reserved bit. In a write, the write value should
R/W ^{always be 0. See table 9.8, for details.}
Table 9.8 MD3 to MD0
Bit 3
MD3*¹
Bit2
MD2*²
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
1
0
0
Phase counting mode 1
1
Phase counting mode 2
1
0
Phase counting mode 3
1
Phase counting mode 4
1
×
×
×
—
Legend:
×: Don’t care
Notes: 1. MD3 is reserved bit. In a write, it should be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
Rev.6.00 Jun. 03, 2008 Page 283 of 698
REJ09B0074-0600