H8S-2218 Datasheet, PDF (395/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 10 Watchdog Timer (WDT)
Writing 0 to WOVF bit
15
87
0
Address: H'FF76
H'A5
H'00
Write to RSTE, RSTS bits
15
Address: H'FF76
H'5A
87
0
Write data
Figure 10.7 Format of Data Written to RSTCSR (Example of WDT0)
Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read by using the
same method as for the general registers. TCSR, TCNT, and RSTCSR are allocated in addresses
H'FF74, H'FF75, and H'FF77 respectively.
10.5.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 10.8 shows this operation.
φ
Address
TCNT write cycle
T1
T2
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 10.8 Contention between TCNT Write and Increment
Rev.6.00 Jun. 03, 2008 Page 347 of 698
REJ09B0074-0600