H8S-2218 Datasheet, PDF (427/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 12 Serial Communication Interface
Bit Bit Name Initial Value R/W Description
3 PER
0
R/(W)* Parity Error
[Setting condition]
• When a parity error is detected during reception
If a parity error occurs, the receive data is transferred
to RDR but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued
while the PER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
[Clearing condition]
• When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
2 TEND 1
R
Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC is activated by a TXI interrupt and
writes data to TDR
1 MPB
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous state
is retained. This bit retains its previous state when the
RE bit in SCR is cleared to 0.
0 MPBT 0
R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
Note:* The write value should always be 0 to clear the flag.
Rev.6.00 Jun. 03, 2008 Page 379 of 698
REJ09B0074-0600