H8S-2218 Datasheet, PDF (645/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 19 Clock Pulse Generator
Bit Bit Name Initial Value R/W Description
2 SCK2 0
R/W System Clock Select 2 to 0
1 SCK1 0
0 SCK0 0
R/W These bits select the bus master clock. To operate in
R/W ^{subactive mode or watch mode, clear the SCK2 to SCK0}
bits to 0.
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11×: Setting prohibited
Legend:
×: Don’t care
19.1.2 Low Power Control Register (LPWRCR)
LPWRCR performs power-down mode control, selects sampling frequency for eliminating noise,
performs subclock oscillator control, and selects whether or not built-in feedback resistance and
duty adjustment circuit of the system clock generator used.
Bit Bit Name Initial Value R/W Description
7 DTON 0
R/W Direct Transition ON Flag
0: When the SLEEP instruction is executed in high-speed
mode or medium-speed mode, operation shifts to sleep
mode, software standby mode, or watch mode*.
When the SLEEP instruction is executed in subactive
mode, operation shifts to subsleep mode or watch mode.
1: When the SLEEP instruction is executed in high-speed
mode or medium-speed mode, operation shifts directly to
subactive mode, or shifts to sleep mode or software
standby mode.
When the SLEEP instruction is executed in subactive
mode, operation shifts directly to high-speed mode, or
shifts to subsleep mode.
Rev.6.00 Jun. 03, 2008 Page 597 of 698
REJ09B0074-0600