H8S-2218 Datasheet, PDF (235/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Figure 7.8 illustrates operation in normal mode.
Address T_A
Transfer
Section 7 DMA Controller (DMAC)
Address T_B
Address B_A
Address B_B
Notes:
Address T_A = L_A
Address T_B = L_B
Address B_A = L_A + SAIDE · (–1)^SAID · (2^DTSZ · (N–1))
Address B_B = L_B + DAIDE · (–1)^DAID · (2^DTSZ · (N–1))
L_A = Value set in MARA
L_B = Value set in MARB
N = Value set in ETCRA
Figure 7.8 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests. With auto-request,
the DMAC is only activated by register setting, and the specified number of transfers are
performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In
cycle steal mode, the bus is released to another bus master each time a transfer is performed. In
burst mode, the bus is held continuously until transfer ends. For setting details, see section 7.3.4,
DMA Controller Register (DMACR).
Rev.6.00 Jun. 03, 2008 Page 187 of 698
REJ09B0074-0600