H8S-2218 Datasheet, PDF (160/750 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 5 Interrupt Controller
5.7 Usage Notes
5.7.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.8 shows an example in which the TGIEA bit in the TPU's TIER_0 is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
TIER0 write cycle by CPU
TGI0A exception handling
φ
Internal
address bus
Internal
write signal
TIER_0 address
TGIEA
TGFA
TGI0A
Interrupt signal
Figure 5.8 Contention between Interrupt Generation and Disabling
Rev.6.00 Jun. 03, 2008 Page 112 of 698
REJ09B0074-0600