SH7136_09 Datasheet, PDF (9/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.2.2 Allocation of DTC Transfer Information
Figure 6 shows the allocation of DTC transfer information in memory.
In this application note, the address H'FFFF8000 is set as the DTC vector base register (DTCVBR) and the vector table
is allocated to an area in the on-chip RAM.
The DTC transfer information is allocated to an area in the on-chip RAM. The SCI receive DTC transfer information is
allocated to address H'FFF8800, and the SCI transmit DTC transfer information is allocated to address H'FFF8810.
The DTC vector base is set in the on-chip RAM area.
DTC vector base register (DTCVBR) = H'FFFF8000
SCI receive DTC
· Activation source: RXI_0 of SCI_0
· Vector number: 217
· DTC vector address offset: H'764
Calculating the DTC vector address
= DTCVBR + DTC vector address offset
= H'FFFF8000 + H'764
= H'FFFF8764
RAM area
H'FFFF8764
（RXI_0）
H'FFFF8768
（TXI_0）
[DTC vector table]
Stores start address for
transfer information (1)
Stores start address for
transfer information (2)
SCI transmit DTC
· Activation source: TXI_0 of SCI_0
· Vector number: 218
· DTC vector address offset: H'768
Calculating the DTC vector address
= DTCVBR + DTC vector address offset
= H'FFFF8000 + H'768
= H'FFFF8768
H'FFFF8800
[DTC transfer information]
Transfer information (1)
(for SCI receive)
H'FFFF8810
Transfer information (2)
(for SCI transmit)
H'FFFF8820
Figure 6 Allocation of DTC Transfer Information in Memory
2.2.3 Operation Description
Figure 7 provides an operation description. The transmit and receive operation setting bits (bits TE and RE) for SCI
channel 0 are set to 1 simultaneously to start transmit and receive operation.
In transmit operation, when 1 byte of data is ready to be transmitted, the TDRE flag is set to 1, a TXI interrupt request
is generated, and the DTC is activated. The DTC transfers the transmit data from the on-chip RAM to the SCI, and the
TDRE flag is automatically cleared to 0. During this time the CPU processes no interrupts. After the specified transfer
count of 32 DTC data transfers is completed, the TDRE flag remains set to 1 and a TXI interrupt is issued to the CPU.
The TDRE flag is cleared to 0 by the interrupt handling routine.
In receive operation, when reception of 1 byte of data finishes, the RDRF flag is set to 1, an RXI interrupt request is
generated, and the DTC is activated. The DTC transfers the receive data to the on-chip RAM, and the RDRF flag is
automatically cleared to 0. During this time the CPU processes no interrupts. After the specified transfer count of 32
DTC data transfers is completed, the RDRF flag remains set to 1 and an RXI interrupt is issued to the CPU. The RDRF
flag is cleared to 0 by the interrupt handling routine.
REJ06B0890-0100/Rev.1.00
July 2009
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