SH7136_09 Datasheet, PDF (8/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.2 Operation of the Sample Program
2.2.1 The Sample Program Operation Specifications
Table 3 lists the SCI communication function settings used in this application note. The SCI performs simultaneous
transmit and receive in clock synchronous mode. The DTC transfer function is used to transfer SCI transmit and receive
data.
Table 3 SCI Communication Function Settings
Item
Module
Communication mode
Interrupts
Communication speed
Transmit/receive data count
Data length
Bit sequence
Synchronization clock
Description
SCI channel 0
Clock synchronous mode
• Transmit data empty interrupt (TXI)
• Receive data full interrupt (RXI)
• Receive error interrupt (ERI)
100 Kbytes
32 bytes
8-bit data (fixed)
LSB-first
Internal clock/synchronization clock output on SCK pin
Table 4 lists the DTC transfer conditions for this application note. The DTC is set to two channels, one for SCI transmit
and one for SCI receive.
Table 4 DTC Transfer Conditions
Item
Transfer mode
Transfer count
Transfer size
Transfer source
Transfer destination
Transfer source
address
Transfer destination
address
Activation source
Interrupt handling
Description
SCI transmit side DTC transfer
conditions (TXI_0)
Normal mode
32 times
Byte transfer
On-chip RAM (SCI transmit data storage
area)
SCI transmit data register (SCTDR_0)
Transfer source address is incremented
following transfer.
Transfer source is fixed.
DTC is activated at SCI channel 0
transmit data empty interrupt (TXI)
request.
Interrupt processing by the CPU (SCI
TXI interrupt) is enabled following the
completion of the specified data transfer
count.
SCI receive side DTC transfer
conditions (RXI_0)
Normal mode
32 times
Byte transfer
SCI receive data register (SCRDR_0)
On-chip RAM (SCI receive data
storage area)
Transfer source is fixed.
Transfer destination address is
incremented following transfer.
DTC is activated at SCI channel 0
receive data full interrupt (TXI) request.
Interrupt processing by the CPU (SCI
RXI interrupt) is enabled following the
completion of the specified data
transfer count.
REJ06B0890-0100/Rev.1.00
July 2009
Page 8 of 22