SH7136_09 Datasheet, PDF (16/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.5 Settings of Registers in the Sample Program
The register setting values used in the reference program are listed below.
2.5.1 Clock Pulse Generator (CPG)
Table 7 shows the register settings for the clock pulse generator (CPG).
Table 7 Clock pulse generator (CPG)
Register Name
Frequency
control register
(FRQCR)
Address
H'FFFFE800
Setting
H'0241
Description
Specifies the operating frequency multiplication
ratios.
• IFC2 to IFC0 = B'000: Internal clock (Iφ) × 1
• BFC2 to BFC0 = B'001: Bus clock (Bφ) × 1/2
• PFC2 to PFC0 = B'001: Peripheral clock (Pφ)
× 1/2
• MIFC2 to MIFC0 = B'000: MTU2S clock (MIφ) × 1
• MPFC2 to MPFC0 = B'001: MTU2 clock (MPφ)
× 1/2
2.5.2 Power-Down Mode
Table 8 shows the register settings for low-power mode.
Table 8 Power-Down Mode
Register Name
Standby control
register_2
(STBCR_2)
Address
H'FFFFE804
Setting
H'28
Standby control
register_3
(STBCR_3)
H'FFFFE806
H'F7
Description
Specifies the operation settings for individual
modules.
• MSTP7 = B'0: Operate RAM.
• MSTP6 = B'0: Operate ROM.
• MSTP4 = B'0: Operate DTC.
Specifies the operation settings for individual
modules.
• MSTP15 = B'1: Stop clock supply to I2C2.
• MSTP13 = B'1: Stop clock supply to SCI_2.
• MSTP12 = B'1: Stop clock supply to SCI_1.
• MSTP11 = B'0: operate SCI_0.
• MSTP10 = B'1: Stop clock supply to SSU.
• MSTP8 = B'1: Stop clock supply to RCAN-ET_0.
REJ06B0890-0100/Rev.1.00
July 2009
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