SH7136_09 Datasheet, PDF (5/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.1.2 Data Transfer Controller (DTC)
The data transfer controller (DTC) can be activated by interrupt requests from on-chip peripheral modules to perform
data transfers.
The DTC has three transfer modes: normal transfer mode, repeat transfer mode, and block transfer mode. By storing
transfer information in a data area, data transfer can be performed using a user-specified number of channels.
When the DTC is activated, the transfer information is read from the data area, data transfer starts, and then updated
transfer information is written back to the data area after the end of the data transfer. The transfer information can be
assigned to a data area in the on-chip RAM or in an external memory space.
For details of the DTC, see the Data Transfer Controller (DTC) section in the SH7137 Group Hardware Manual
(RJJ09B0392).
Table 2 shows an overview of the DTC. Figure 3 is a block diagram of the DTC.
Table 2 Overview of DTC
Item
Description
Transfer modes
• Three transfer modes
• Normal transfer mode
• Repeat transfer mode
• Block transfer mode
Transfer count
• Normal transfer mode: 1 to 65,536
• Repeat transfer mode: 1 to 256
• Block transfer mode: 1 to 65,536
Data size
The data size for data transfers may be set to byte, word, or longword.
CPU interrupt
requests
• An interrupt request can be set to the CPU at the end of a single data transfer.
• An interrupt request can be set to the CPU at the end of a specified number of
data transfers.
Others
• Support for chain transfer (multiple data transfers triggered by a single activation
source)
• Support for transfer information read skip mode
• Support for skipping write-back for fixed transfer source addresses and transfer
destination addresses
• Support for module stop mode
• Support for short address mode
• Selectable among five bus right release timings
• Selectable between two priorities at DTC startup
Note: An on-chip peripheral module should be set as, at a minimum, either the transfer source or transfer
destination. The DTC cannot be used for transfers among external memory, memory mapped
external devices, and on-chip memory only.
REJ06B0890-0100/Rev.1.00
July 2009
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