SH7136_09 Datasheet, PDF (13/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.4.3 Initialization of Data Transfer Controller (DTC)
Figure 10 shows the initial setting sequence for the data transfer controller (DTC).
DTC settings
for SCI receive
(DTC_RXI0)
DTC settings
for SCI
transmit
(DTC_TXI0)
dtc_init()
Make settings in DTC control
[1]
register (DTCCR)
Make settings in DTC mode
register A (MRA)
[2]
Make settings in DTC mode
register B (MRB)
[3]
Make setting in DTC source
address register (SAR)
[4]
Make setting in DTC destination
address register (DAR)
[5]
Make setting in DTC transfer count
register A (CRA)
[6]
Make setting in DTC transfer count
register B (CRB)
[7]
Make settings in DTC mode
[8]
register A (MRA)
Make settings in DTC mode
[9]
register B (MRB)
Make setting in DTC source
address register (SAR)
[10]
Make setting in DTC destination
address register (DAR)
[11]
Make setting in DTC transfer count
register A (CRA)
[12]
Make setting in DTC transfer count
register B (CRB)
[13]
Make setting in DTC vector base _[14]
register
Make vector table settings
[15]
Make settings in DTC enable
register E (DTCERE)
[16]
END
[1] Operating mode selection
· RRS bit = B'0: No not skip reading DTC transfer information.
· RCHNE bit = B'0: Disable chain transfer after repeat transfer.
· ERR bit = B'0: Clear transfer stop flag.
DTC transfer information (DTC_RXI0) settings for SCI receive
[2] Operating mode A selection
· MD bit = B'00: Normal transfer mode
· Sz bit = B'00: Byte size transfer
· SM bit = B'00: SAR is fixed.
[3] Operating mode B selection
· CHNE bit = B'0: Disable chain transfer.
· DISEL bit = B'0: Enable interrupt after end of specified
transfer count.
· DM bit = B'10: Increment DAR after transfer.
[4] Transfer source address setting
Specify SCI receive data register_0 (SCRDR_0).
[5] Transfer destination address setting
Specify SCI receive data storage area (start address)
(on-chip RAM).
[6] Data transfer count: 32 times
[7] Specify block data transfer count (not used): 0 times
DTC transfer information (DTC_TXI0) settings for SCI transmit
[8] Operating mode A selection
· MD bit = B'00: Normal transfer mode
· Sz bit = B'00: Byte size transfer
· SM bit = B'10: Increment SAR after transfer.
[9] Operating mode B selection
· CHNE bit = B'0: Disable chain transfer.
· DISEL bit = B'0: Enable interrupt after end of transfer.
· DM bit = B'00: DAR is fixed.
[10] Transfer source address setting
Specify SCI transmit data storage area (start address)
(on-chip RAM).
[11] Transfer destination address setting
Specify SCI transmit data register_0 (SCTDR_0).
[12] Set data transfer count: 32 times
[13] Specify block data transfer count (not used): 0 times
[14] DTC vector base register setting
Allocate DTC vector table in on-chip RAM.
[15]
· Set DTC transfer information (DTC_RXI0) for SCI receive
in vector table.
· Set DTC transfer information (DTC_TXI0) for SCI transmit
in vector table.
[16] DTC interrupt vector settings
· Enable DTC activation by SCI_0 interrupt source RXI_0.
· Enable DTC activation by SCI_0 interrupt source TXI_0.
Figure 10 Initialization of Data Transfer Controller (DTC)
REJ06B0890-0100/Rev.1.00
July 2009
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