SH7136_09 Datasheet, PDF (17/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.5.3 Interrupt Controller (INTC)
Table 9 shows the register settings for the interrupt controller (INTC).
Table 9 Interrupt Controller (INTC)
Register Name Address
Setting
Description
Interrupt priority H'FFFFE992 H'F000
register L (IPRL)
Sets interrupt priority levels (level 0 to 15).
• Bits 15 to 12 = B'1111: SCI_0 interrupt level = 15
• Bits 11 to 8 = B'0000: SCI_1 interrupt level = 0
• Bits 7 to 4 = B'0000: SCI_2 interrupt level = 0
• Bits 3 to 0: Reserved
The SCI_0 interrupt is used by the reference
program.
Note: The SCI0 RXI and TXI interrupt priority is according to the offset address order of the interrupt vector
addresses. For details on interrupt priority, see the Interrupt Exception Handling Vector Table item in
the Interrupt Controller section of the SH7137 Group Hardware Manual.
2.5.4 Pin Function Controller (PFC)
Table 10 shows the register settings for the pin function controller (PFC).
Table 10 Pin Function Controller (PFC)
Register Name
Port E control
register L1
(PECRL1)
Address
H'FFFFD316
Setting
H'6660
Description
Sets port E multiplexed pin functions.
• PE3MD2 to PE3MD0 = B'110: PE3 functions as
SCK0 I/O (SCI).
• PE2MD2 to PE2MD0 = B'110: PE2 functions as
TXD0 output (SCI).
• PE1MD2 to PE1MD0 = B'110: PE1 functions as
RXD0 input (SCI).
• PE0MD1 and PE0MD0 = B'00: PE0 functions as
PE0 I/O (port).
REJ06B0890-0100/Rev.1.00
July 2009
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