SH7136_09 Datasheet, PDF (18/22 Pages) Renesas Technology Corp – SCI Clock Synchronous Simultaneous Transmit and Receive of Serial Data and DTC Data Transfer

SH7136/SH7137 Group
SCI Clock Synchronous Simultaneous Transmit and
Receive of Serial Data and DTC Data Transfer
2.5.5 Data Transfer Controller (DTC)
Tables 11, 12, and 13 list the DTC settings for this application note.
Table 11 Data Transfer Controller (DTC) Common Settings
Register Name
DTC control
register
(DTCCR)
Address
Setting
H'FFFFCC90 H'00
DTC vector base
register
(DTCVBR)
DTC enable
register
E(DTCERE)
H'FFFFCC94
H'FFFFCC88
H'FFFF8000
H'C000
Description
• RRS = B'0: No not skip reading transfer
information.
• RCHNE = B'0: Disable chain transfer.
• ERR = B'0: No interrupt requests.
Specify the on-chip RAM area as the base address
used to calculate vector table addresses.
Select the interrupt source that activates the DTC.
• DTCERE15 = B'1: Select RXI_0 as the activation
source.
• DTCERE14 = B'1: Select TXI_0 as the activation
source.
Table 12 DTC Transfer Information (DTC_RXI0) for SCI Receive
Register Name Address
Setting
Description
DTC mode
H'FFFF8800 H'00
register A(MRA) *¹
• MD1 and MD0 = B'00: Normal transfer
• Sz1 and Sz0 = B'00: Byte size transfer
• SM1 and SM0 = B'00: SAR is fixed.
DTC mode
H'FFFF8801 H'08
register B(MRB) _{(MRA +1)}
• CHNE = B'0: Disable chain transfer.
• CHNS = B'0: Continuous chain transfer.
• DISEL = B'0: Generate CPU interrupt request at
end of specified data transfer count.
• DTS = B'0: Set destination as repeat area or block
area.
• DM1 and DM0 = B'10: Increment DAR.
DTC source
H'FFFF8804
address register (MRA +4)
(SAR)
SCRDR_0
Register
Specify transfer source address.
Set SCI0 receive data register_0 (SCRDR_0).
DTC destination
address
register(DAR)
H'FFFF8808
(MRA +8)
On-chip
RAM*²
Specify transfer destination address.
Store start address of buffer array variable for receive
(&rxi0_data[0]).
DTC transfer
count register
A(CRA)
H'FFFF880C H'0020
(MRA+12)
Specify DTC data transfer count.
32 times
DTC transfer
count register
B(CRB)
H'FFFF880E H'0000
(MRA+14)
Specify DTC block data transfer count for block
transfer mode (not used).
Notes: 1. The transfer information is allocated to on-chip RAM as a structure variable with no initial value.
The allocation of variables in memory is dependent on the section allocation settings of the
optimizing linkage editor used to create the executable object code.
2. The array variables are allocated to on-chip RAM as variables with no initial value. The allocation
of variables in memory depends on the results of the compile process used to generate the
executable object code.
REJ06B0890-0100/Rev.1.00
July 2009
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