H8S2194 Datasheet, PDF (85/1078 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 2 CPU
Note that the first part of the address range is also the exception vector area. For further details,
see section 5, Exception Handling.
Specified by
@aa:8
Branch address
Specified by
@aa:8
Reserved
Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or an instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
2.7.2 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode.
In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit
address.
Rev.3.00 Jan. 10, 2007 page 49 of 1038
REJ09B0328-0300