H8S2194 Datasheet, PDF (159/1078 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 Interrupt Controller
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
6.5.2 Instructions That Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts except NMI are disabled and the next instruction is always
executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
6.5.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
6.5.4 When NMI Is Disabled
When NMI is disabled, the input level to the NMI pin must be fixed high or low. It is
recommended that the NMI interrupt exception handling address be set to the NMI vector address
(H'00001C to H'00001F) and that the RTE instruction also be set to the NMI exception handling
address.
Rev.3.00 Jan. 10, 2007 page 123 of 1038
REJ09B0328-0300