H8S2194 Datasheet, PDF (110/1078 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 4 Power-Down State
4.2 Register Descriptions
4.2.1 Standby Control Register (SBYCR)
Bit :
7
6
5
4
3
SSBY STS2 STS1 STS0
—
2
1
0
—
SCK1 SCK0
Initial value :
0
0
0
0
0
R/W : R/W
R/W
R/W
R/W
—
0
0
0
—
R/W
R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset.
Bit 7⎯Software Standby (SSBY): Determines the operating mode, in combination with other
control bits, when a power-down mode transition is made by executing a SLEEP instruction. The
SSBY setting is not changed by a mode transition due to an interrupt, etc.
Bit 7
SSBY
0
1
Description
Transition to sleep mode after execution of SLEEP instruction in high-speed mode
or medium-speed mode
Transition to subsleep mode after execution of SLEEP instruction in subactive
mode
(Initial value)
Transition to standby mode, subactive mode, or watch mode after execution of
SLEEP instruction in high-speed mode or medium-speed mode
Transition to watch mode or high-speed mode after execution of SLEEP instruction
in subactive mode
Rev.3.00 Jan. 10, 2007 page 74 of 1038
REJ09B0328-0300