H8S2194 Datasheet, PDF (1029/1078 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

H'FFBB: Timer Counter A TCA: TimerA
Appendix B Internal I/O Registers
Bit :
Initial value :
R/W :
7
TCA7
0
R
6
TCA6
0
R
5
TCA5
0
R
4
TCA4
0
R
3
TCA3
0
R
2
TCA2
0
R
1
TCA1
0
R
0
TCA0
0
R
H'FFBC: Watchdog Timer Control/Status Register WTCSR: WDT
Bit :
Initial value :
R/W :
7
OVF
0
R/(W)^*
6
WT/IT
0
R/W
5
TME
0
R/W
4
3
2
RSTS RST/NMI CKS2
0
0
0
R/W R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Reset or NMI
0
NMI interrupt request is disabled
1
Internal reset request is generated
Timer enable bit
0
WTCNT is initialized to H'00 and halted
1
WTCNT counts
Timer mode select bit
0
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when WTCNT overflows
1
Watchdog timer mode: Sends the CPU a reset or NMI interrupt
request when WTCNT overflows
Overflow flag
0
[Clearing conditions]
(1) Write 0 in the TME bit
(2) Read WTCSR when OVF = 1, then write 0 in OVF
1
[Setting condition]
When WTCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.)
Note: * Only 0 can be written to clear the flag.
Rev.3.00 Jan. 10, 2007 page 993 of 1038
REJ09B0328-0300