3822_03 Datasheet, PDF (84/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.2 Interrupts
(3) Timing after acceptance of an interrupt request
The interrupt processing routine is started at the timing of machine cycle after completion of the
executing instruction. Figure 2.2.3 shows the processing time up to the execution of an interrupt
processing routine and Figure 2.2.4 shows timing after the acceptance of an interrupt request.
Interrupt request occurs
Interrupt operation starts
Main routine
V
Waiting time
for pipeline post-
processing
V
Push onto stack
Vector fetch
Interrupt processing routine
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles
(At internal system clock φ = 3.15 MHz, 2.2 µ s to 7.3 µ s)
V : Refer to “Figure 2.2.4”
Fig. 2.2.3 Processing time up to execution of interrupt processing routine
Waiting time for pipeline
postprocessing
φ
Push onto stack
Vector fetch
Interrupt operation starts
SYNC
RD
WR
Address bus
PC
S, SPS S-1, SPS S-2, SPS _{BL BH AL, AH}
Data bus
Not used PCH PCL PS AL AH
SYNC : CPU operation code fetch cycle
(This is an internal signal which cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt (Note)
SPS : “0016” or “0116”
Note: Refer to “Table 6 in CHAPTER 1 HARDWARE .”
Fig. 2.2.4 Timing after acceptance of interrupt request
2–18
3822 GROUP USER’S MANUAL